This application is related to commonly assigned, application Ser. No. 09/387,146 (99-AD-081) filed concurrently herewith and incorporated herein by reference.
This invention relates generally to digital signal processing devices and specifically to an efficient interpolator for high speed timing recovery.
In most communication and storage systems, timing (or clocking) information is extracted from the received signal. This recovered timing information is often used to resample the received signal such that the detector in such a system can operate on samples that are synchronous to the data being received. This recovery is often achieved using a sampling device, such as an analog-to-digital converter (ADC) or a sample and hold (S/H) circuit.
Both the ADC and the S/H circuit use a reclocking signal to sample a continuous waveform. The clock input of such a system is usually obtained from a voltage controlled oscillator (VCO). The input signal controlling the VCO frequency can be used to change the sampling point on the continuous waveform.
In digital systems it is often desirable to sample the signal with an asynchronous clock and use digital signal processing to process the signal and recover the timing information. Such a system is described in papers by Gardner. Floyd M. Gardner, xe2x80x9cInterpolation in Digital Modems-Part I: Fundamentals, IEEE Transactions on Communications, 41(6), June 1993, and Floyd M. Gardner, xe2x80x9cInterpolation in Digital Modems-Part II: Implementation and Performance, IEEE Transactions on Communications, 41(6), June 1993.
The use of digital signal processing avoids the requirement of analog components in the timing recovery loop. Also digital processing, such as equalization, can be achieved before the timing information is recovered.
An important function of such a digital timing recovery system is a variable interpolator. This function produces an output signal which is a time shifted version of the input signal. The time shift is determined from a programmable input which in a timing recovery application may be required to change on a sample to sample basis. In particular, a frequency shift can be achieved by having a continuously varying time delay on the input.
FIG. 1 shows a block diagram of an interpolator 10. Interpolator 10 receives a sequence of input signals X(kT) and time shifts this sequence by a time xcfx84k. The output of interpolator 10 provides a sequence of signals Y(kTxe2x88x92LT+xcfx84k-m). In practice the time shift input xcfx84k can adjust the delay over a limited range, usually one sample period T. Typically 0xe2x89xa6xcfx84 less than T or xe2x88x92T/2xe2x89xa6xcfx84 less than T/2.
A basic discrete time interpolation function can be implemented as shown in FIG. 2. The interpolator 10 includes a finite impulse response (FIR) filter 12 and a read only memory
FIR filter 12 receives input sequence Xk, which is applied to a group of serially coupled delay elements 16. Each delay element 16 provides an output that is one clock cycle delayed from its input. The timed sequence of signals X is provided to each of a number of multipliers 18. The multipliers receive a second input from ROM 14 and provide the results to summer (or adder) 20. The output of summer 20 is the sequence of signals Yk.
In operation, the time shifting is achieved by FIR filter 12. In order to provide a time shift to the input signal, the coefficients of the filter 12 should be a sin c function. In particular, for a time shift of xcfx84 the coefficients hk should be
hk=sin c(k+xcfx84) where k=xe2x88x92∞, . . . , xe2x88x921, 0, 1, . . . , ∞
where the sin c function is defined as
sin c(x)=sin(xcfx80x)/xcfx80x.
While an ideal interpolator response extends over an infinite length of time, in practice, the filter length will be truncated to a practical length. This can be achieved in particular when the system is oversampled or the energy in the signal is not spread equally over the whole signal band.
The coefficients of the filter change depending on the required time shift xcfx84 and may be calculated or looked up in a lookup table implemented by read only memory 14. FIG. 2 shows a ROM based lookup table. In this case, the number of possible values of xcfx84 is limited by the size of the ROM 14.
Recently a cost reduced interpolation scheme has been described in U.S. Pat. No. 5,760,984 issued Jun. 2, 1998 and entitled xe2x80x9cCost Reduced Interpolated Timing Recovery in a Sampled Amplitude Read Channel,xe2x80x9d incorporated herein by reference. This interpolator uses three parallel prefilters and a three-tap interpolator.
In one aspect, the present invention provides an efficient implementation of an interpolation system that could be used in high speed timing recovery systems. The interpolator is intended for use in such systems as sampled magnetic recording read channels but may also be used in other high speed digital storage and communications channels, where sampling at close to, or equal to, the baud rate is required.
In a first aspect, the present invention discloses an interpolation circuit that includes n multipliers. Each multiplier receives inputs from a coefficient memory and a select circuit. The select circuit receives its inputs from a plurality of input nodes. These input nodes are taken from a digital data stream, possibly after some prefiltering. The select circuit is configured so that at a first time each of the input nodes is coupled to a respective one of the output nodes of the select circuit and such that at a second time at least some of the input nodes are coupled to a different one of the output nodes of the select circuit. In some embodiments, inclusion of the select circuit allows the size of the coefficient memory to be reduced.
In another aspect, the present invention provides a data processing circuit that can be used, for example, in a data recovery scheme. A digital data source outputs a sequence of digital signals. These digital signals are spaced by a time period. A pre-filter receives the digital signals and provides a second sequence of digital signals. The second sequence of digital signals is spaced by a second time period that is smaller than the first time period. An interpolation circuit receives the second sequence of digital signals and can operate on them. In one aspect, the interpolation circuit operates on five input signals at a time but does so with less than five multipliers.
The quality of an interpolator as disclosed here can be judged by a number of properties. For example, accuracy provides an indication of how closely the implementation matches an ideal interpolator. Another factor is latency. When used in a timing recovery loop, the loop acts to change the timing phase of the interpolator based on the output samples. Therefore, it is important to minimize the time delay (latency) between changing the time shift input and the output samples reflecting this change to improve the stability of the loop.
It is also desirable to minimize the complexity of the interpolator implementation to allow small area and power dissipation when implemented in hardware. It is also desirable to achieve an implementation that allows high speed operation. The speed factor is especially important in magnetic recording applications where high speed is required where the signal may be sampled at or close to the baud rate of the signal.
The interpolation scheme of the present invention provides advantages in each of these areas. For example, the latency and speed of the circuit is improved. Since the interpolator requires fewer multipliers and adders, the delay between the input and output is reduced. In addition, the ROM complexity is significantly reduced allowing for faster operation.
The complexity of the system is also reduced because of the reduced number of multipliers and adders in the interpolation section. The lower complexity results in lower power and smaller area in an integrated circuit implementation.